Get help from the best in academic writing.

Tokyo Midtown’s Architecture Development

The Tokyo Midtown was built between 2004-2007, which is a 101,000 square meter mixed-use development located in Roponggi, Tokyo, Japan. This project design was begun on August 2002 and the construction of the project was begun on May 2004 and completed on March 2007. There is a 400-year-old Hinokicho Park within the site was refurbished. The U.S. Army was stayed in this site as a barrack during World War II, the Japanese Defense Agency occupied this site after the army left. Consequently, Japanese Government sold the site in 2001 and Mitsui Fudosan won it. There was an archaeological exploration conducted during 2002 and 2003. During the exploring period, over fifty thousand pieces of pottery and two pieces of gold coins from Edo-period (1596-1698) were found out. The mixed-use development includes office, residential, retail, hotel, museum and leisure space. The total floor area of the development is 563, 800 square meters. There are over 50% of the project is designed to be open space.
Tokyo Midtown is located at two main street roads in roponggi district, there is a large lawn included in the site. Besides the class A office, residential units, High-end retail and hotel, and the museum, there is 50 percentage of site area are parks, plazas, promenades and streetscapes. In Tokyo, green space is only a private garden or scared space. The definition of green space is different from other cities. The green space used to be appreciated rather than utilizing. Citizens are not encouraged to use the green space and public events are not promoted to happen in such area. The primary developer, Mitsui Fudosan would like to change this old mind of green area and bring the new trend of Green Park. Thus, Tokyo Midtown was designed to be the new urban oasis in Roponggi district.
Imperial Palace is not only the largest public open space in Tokyo, but also a good case to show the typology of traditional Japanese landscape. The parkland of Imperial Palace is surrounded by the wall, which isolates the palace from the city’s context. The cultural and historical valuable of the palace was abandoned, that the landscape of palace is cut off by the wall as an island, and there is no associated development next to the palace. This kind of traditional landscape promotes privacy and peaceful rather than connection between urban context. The developer would like to introduce a new landscape typology to the city. His approach is to create a unique sequence of open space which is new trend of connective landscape.
The project’s developer promotes a new Japanese landscape design by creating a unique urban movement in the complex. The Tokyo Midtown a welcoming and attractive space which can stimulate the social and cultural interaction, thus the life of the place will be activated. This project is an architectural expression in landscape which can provide an open and green space for events. The historical green space Hinokicho Park is part of landscape and was refurbished. There are mainly three primary movements for the landscape in Tokyo Midtown. Firstly, the existing park is extended to the newer green areas. Secondly, there are a series of water features begin at the plaza. Thirdly, the water features flow down toward the greenery.
There were 40 mature cherry trees preserved from the old site and transplanted on new site. Those trees are used to create a new cherry promenade by connecting the entry to Hinokicho Park. There are over thousands of visitors attracted to here for gathering and celebrating the cule of seasons, during the blossom season of cherry.
In recent years, podium type development becomes the main new typology of large-scale development, especially in Hong Kong. The advantage of this typology is to provide a convenient and efficient connection from the upper level to the mass transit by the footbridge network. However, this typology has been produced less vibrant street life. The functional relationship between building and urban street grid has been lost. The public space has been separated from the existing neighborhood, thus the development has been isolated from urban street. Tokyo Midtown is a successful large-scale development with podium and tower that diminish the drawback of podium design. It undertakes a more sustainable approach to the new large-scale development. The development of Tokyo Midtown has achieved the sustainable design approach by several criteria as below:
First of all, the development of Tokyo Midtown took the opportunity to integrate this new development into the existing areas by creating great places which can improve the original district and bring a long-term value. This place-making approach is achieved by promoting the public spaces with landscape. The sense of space is created by adding the attractive street furniture and public art in the landscape, such as the lush mature tree canopy in the entrance. This canopy can emphasize the existing site characteristic and enhance the site’s cultural and historical value. The landscape design improves the flexibility of space, so that public and private events will be promoted in order to facilitate the social interaction and vitality in this place. For example, the cherry promenade provides the linkage to the Hinokicho Park and also a place for gathering and celebrating the beauty of the trees during the bloom season. Thousands of visitors attract by it and go there with a blanket, picnic, and drinks. The high quality design of Tokyo Midtown activates the existing space and brings economic incomes, and reflects the character of the surrounding area. This mix-used development incorporated hotel, office, residential, retail, restaurants, museum and parks. It provides a small community for people to live, work and enjoy their leisure time. Besides, the Tokyo Midtown introduces the pedestrian connectivity in both physical and psychological way. Visitors can experience a rich and vibrant pedestrian through visiting the tree-lined street and pleasant walkway. The lining of trees refurbishes the existing subway stop and redirects the ground passenger to the new exit at Tokyo Midtown. The place-making approach is also strengthened by providing high-quality public realm. It lets wide range of activities happen in this area. The unique identity landmarks, the 54 storeys Mori Tower has been incoporated in the whole development which is the tallest building in Tokyo. It increases the attractiveness of the destination.
Secondly, Tokyo Midtown has well integrated with the infrastructure and the surrounding transport network. It provides a high standard connection to the transit and improves the connection between site and surrounding area at the ground level. Tokyo Midtown is not a project only concern the spatial quality within the site boundary, but also to provide the mix-used development with a wider site context and great impact on surrounding area. Citizens criticize that walled developments issue would be raised as the project with infrastructure is easily being isolated from the urban due to the poor integration of surrounding. This project includes 5 buildings, a high-end retail, luxury department, class A office space, luxury department, medical center. These 5 buildings surround a skyscraper with 248m height. The whole development is well integrated to the adjacent park and the Roppongi railway station. Roppongi railway station is a famous station along the Toei Oedo Line. Tokyo Midtown provides a successful access to the exit of railway station through the spatial arrangement of the open space. There is good public transport connection provided. The Roppongi railway station is well connected to the public transport interchanges within the Tokyo Midtown. The site is quite near the Roppongi Hills development which is less than 0.8 kilometer. The Roppongi Hill is surrounded by the vehicle-dominated road infrastructure and connects to podium of Tokyo Midtown. The majority of the edges are connected to the street level, it breaks down the traditional podium language. This project has well integration between land use and the transport in both physical and social aspects.
Sustainable strategy
Large-scale development usually bring negative impact on surrounding area or the wider context, as developer usually only focus on designing the area within the site, the adjacent area may not be their concern. Tokyo Midtown is a large-scale development which has been well integrated with the surrounding area. The design of this project is base on the sustainable development principles and the urban design guidelines, so that it will keep integrating and sustainable in a long-term period. The resource efficiency and environmental friendly approach is also adopted in development. The floor area of the whole development is concentrated in one quadrant of the site, so that the urban park area can be maximized. There is more than 40 percent of the site area is designed as an urban park which act as a main connection between the site and the community greenbelt. Tokyo Midtown promotes sustainability at the neighborhood and district levels, the spatial quality of the pedestrian environment at the street level is enhanced. As a result, the walkability and the livability within the site area and also the district are gradually improved. The location and proportion of program of the whole development is concerned to improve the sustainability in environmental, social and economic aspect. There are over 150 shops and restaurants offered in the high-end retail area, 500 luxury residential units, several office towers, a Ritz-Carlton hotel, 800-seat conservation center and an art museum provided in development, which can benefit the district in social and economic way. The large green open space which occupies 40 percent of site area can benefit the district in environmental way. The open space is designed to guide visitor walk from surrounding streets and sidewalk to the site. A sense of “on the ground” is promoted by touching the earth and nature. There are some view corridors, transparent material, bridges and plazas visually open and connect to the open space in order to lead the visitor from the park to the nature. The design of water feature is to lead the visitors to the park and guide them down though meandering pathway to the 21_21 Design Museum and the traditional Japanese Garden.
New district ‘s image
Before the completion of Tokyo Midtown, Roppongi was a well-known district as a night town. Roponggi was a place which is full of entertainment hub and with abandoned traditional neighborhood. The developer Mitsui Fudosan would like to change the public perception of Roppongi district from a night town to an update image which is a vitalized daytime district. Tokyo Midtown is a development to provide a balance mix of business and living place to the district, in which the cultural amenities will be highly respected. Moreover, Tokyo Midtown is a hope as business and economy revival of Japan, it designed to represent the best characteristic of Japanese society by the mixed-use development. The Japanese government treats it as a priority urban redevelopment area”. This mixed-use development has integrated with a public park , which promotes an environmental friendly and commercial active attraction in this district, thus it benefit to the entire neighborhood and enhance the economic value of Roppongi. To match with this large green park, the famed Suntory Museum of Art was relocation. Consequently, the green park, museum, Tokyo National Art Center and Roppongi Hill will be well connected. The community park is merged with the existing greenbelt and connects to those abandoned nearby green space such as the gorunds of Tokyo government cemetery and a Shinto religious shrine.

Single-Instruction Stream Multiple-Data Stream Architecture

Introduction to SIMD Architectures
SIMD (Single-Instruction Stream Multiple-Data Stream) architectures are essential in the parallel world of computers. Their ability to manipulate large vectors and matrices in minimal time has created a phenomenal demand in such areas as weather data and cancer radiation research. The power behind this type of architecture can be seen when the number of processor elements is equivalent to the size of your vector. In this situation, componentwise addition and multiplication of vector elements can be done simultaneously. Even when the size of the vector is larger than the number of processors elements available, the speedup, compared to a sequential algorithm, is immense. There are two types of SIMD architectures we will be discussing. The first is the True SIMD followed by the Pipelined SIMD. Each has its own advantages and disadvantages but their common attribute is superior ability to manipulate vectors.
True SIMD: Distributed Memory
The True SIMD architecture contains a single contol unit(CU) with multiple processor elements(PE) acting as arithmetic units(AU). In this situation, the arithmetic units are slaves to the control unit. The AU’s cannot fetch or interpret any instructions. They are merely a unit which has capabilities of addition, subtraction, multiplication, and division. Each AU has access only to its own memory. In this sense, if a AU needs the information contained in a different AU, it must put in a request to the CU and the CU must manage the transferring of information. The advantage of this type of architecture is in the ease of adding more memory and AU’s to the computer. The disadvantage can be found in the time wasted by the CU managing all memory exchanges.
True SIMD: Shared Memory
Another True SIMD architecture, is designed with a configurable association between the PE’s and the memory modules(M). In this architecture, the local memories that were attached to each AU as above are replaced by memory modules. These M’s are shared by all the PE’s through an alignment network or switching unit. This allows for the individual PE’s to share their memory without accessing the control unit. This type of architecture is certainly superior to the above, but a disadvantage is inherited in the difficulty of adding memory.
Pipelined SIMD
Pipelined SIMD architecture is composed of a pipeline of arithmetic units with shared memory. The pipeline takes different streams of instructions and performs all the operations of an arithmetic unit. The pipeline is a first in first out type of procedure. The size of the pipelines are relative. To take advantage of the pipeline, the data to be evaluated must be stored in different memory modules so the pipeline can be fed with this information as fast as possible. The advantages to this architecture can be found in the speed and efficiency of data processing assuming the above stipulation is met.
SIMD BASICS
Early microprocessors didn’t actually have any floating-point capabilities; they were strictly integer crunchers.? Floating-point calculations were done on separate, dedicated hardware, usually in the form of a math coprocessor.? Before long though, transistor sizes shrunk to the point where it became feasible to put a floating-point unit directly onto the main CPU die, and the modern integer/floating-point microprocessor was born.? Of course, the addition of floating-point hardware meant the addition of floating-point instructions.? For the x86 world, this meant the introduction of the x87 floating-point architecture and its (now hopelessly archaic) stack-based register model.
Actually, the addition of SIMD instructions and hardware to a modern, superscalar CPU is a bit more drastic than the addition of floating-point capability.? A microprocessor is a SISD device (Single Instruction stream, Single Data stream), and it has been since its inception.
As you can see from the above picture, a SIMD machine exploits a property of the data stream called data parallelism.? You get data parallelism when you have a large mass of data of a uniform type that needs the same instruction performed on it.? A classic example of data parallelism is inverting an RGB picture to produce its negative.? You have to iterate through an array of uniform integer values (pixels), and perform the same operation (inversion) on each one — multiple data points, a single operation.? Modern, superscalar SISD machines exploit a property of the instruction stream called instruction-level parallelism (ILP).? In a nutshell, this means that you execute multiple instructions at once on the same data stream.? (See my other articles for more detailed discussions of ILP).? So a SIMD machine is a different class of machine than a normal microprocessor.? SIMD is about exploiting parallelism in the data stream, while superscalar SISD is about exploiting parallelism in the instruction stream.
There were some early, ill-fated attempts at making a purely SIMD machine (i.e., a SIMD-only machine).? The problem with these attempts is that the SIMD model is simply not flexible enough to accoodate general purpose code.? The only form in which SIMD is really feasible is as a part of a SISD host machine that can execute conditional instructions and other types of code that SIMD doesn’t handle well.? This is, in fact, the situation with SIMD in today’s market.? Programs are written for a SISD machine, and include in their code SIMD instructions.
SIMD Machines
The three SIMD machines covered in this paper are the Connection Machine by Danny Hillis, the Abacus Project at the MIT AI Lab, and the CAM-8 machine by Norman Margolus. These three machines give a pretty accurate sampling of the type of SIMD machines that were constructed as well as an idea of the motivations for creating the machines in the first place.
The Connection Machine was composed of 65,536 bit processors. Each die consisted of 16 processors with each processor capable of communicating with each other via a switch. These 4,096 dies formed the nodes of a 12th dimension hypercube network.
Thus, a processor was guaranteed to be within 12 hops of any other processor in the machine. The hypercube network also facilitated communication by providing alternative routes from source processor to destination. Each node was given a 12-bit node ID, and different paths between two nodes in the network could be traversed based on how the node ID was read. The network allowed for both packet and circuit-based communication for flexibility.
The second machine discussed is the Abacus machine created at the MIT AI Lab. This machine was constructed primarily for vision processing. The machine consisted of 1024 bit processing elements set in a 2D mesh. The primary concept of interest from the design was that the processing elements were configurable, and used reconfigurable bit parallel “RBP” algorithms instead of traditional bit serial computation. This means that each PE emulated logic for part of an arithmetic circuit (be it an adder, shifter, multiplier,etc) based on a RBP algorithm. The motivation for having these configurable processingelements was to save on the silicon area needed to implement arithmetic. However,because there was a necessary overhead for reconfiguration and the implementation did not easily allow for pipelining due to data dependencies, it was not clear that having configurable processing elements was a definite win.
SIMD versus Loop Pipelining
We can consider two different models for mapping loops onto coarse-grained reconfigurable architecture – SIMD and loop pipelining. SIMD computation model is efficient for computation intensive,data-parallel applications requiring less context words to configure reconfigurable processing elements. Since data load and computation are temporarily separated in this model,
array elements are not efficiently utilized. In the case of loop pipelining, different operations in a loop can be executed simultaneously in a pipeline. With this flexibility, data load and computation can be simultaneously executed and all reconfigurable array elements can be efficiently used. In some loops, the performance of pipelining is roughly the same as the performance of SIMD. However, if a loop has frequent memory operations, the pipelining will render much higher performance.
Reconfigurable Architecture
The reconfigurable architecture that we propose consists of an ARM 926EJ-S processor, an SDRAM, a DMA controller, and a coarse-grained Reconfigurable Core Module (RCM) template, which is similar to Morphosys and specified in the DSE flow. The communication bus is AMBA AHB ,which couples the ARM 926EJ-S processor and the DMA controller as master devices and the RCM as a slave device. The ARM 926EJ-S processor executes control intensive, irregular code segments and the RCM executes data-intensive, kernel code segments.
Design Space Exploration
The design space exploration (DSE) flow of coarse-grained reconfigurable architecture. A design starts from profiling and partitioning of target application and defining an architecture from the tem plate. Data intensive, regular loops are selected from the profiling result and the rest of the application is modified to take care of synchronization. The selected loops are analyzed to determine the RCM structure from the template and the configuration words are generated. Design space exploration flow From the architecture specification, we can generate a SystemC description for fast architecture evaluation . Then the loop pipelining model is applied to the SystemC description. Binary configuration data are included in the executable code and overall performance of the application is evaluated on the transaction level platform. The transaction level modeling enables fast design space exploration at early stage . Finally, the architecture is designed at the RT level from the SystemC model and the performance is evaluated on the RTL platform. The RTL architecture is verified by FPGA prototyping.
RCM Template Architecture
RCM specification starts from the template architecture similar to Morphosys. Whereas the memory structure (frame buffer and configuration cache) of Morphosys support only the SIMD model, we support both SIMD and pipelining by modifying the memory structure.
Types of memory:-
Frame Buffer
Frame buffer (FB) of Morphosys does not support concurrency between the load of two operands and the store of result in a same column. It is not needed in SIMD mapping. However, in the case of loop pipelining, concurrent load and store operations can happen between mapped loop iterations. So we modified the FB and bit-width of data bus is specified in the DSE flow. We simply added a bank to each set. Therefore, a bank can be connected to the write bus while the other two banks are connected to the read buses. Any combination of one-to-one mapping between the three banks and the three buses is possible.
Configuration Cache
Context memory of Morphosys is designed for broadcast configuration. So RCs in the same row or column share the same context word for SIMD operation. However, in the case of loop pipelining, each RC can be configured by different context word. So we modified the context memory and designated it as Configuration Cache. Configuration cache is composed of 64 Cache Elements(CE) and Cache Control Unit(CCU) for controlling each CE. Each CE has enough layers that enable dynamic reconfiguration and the number of layers is specified in the DSE flow. CCU supports 4 configuration modes(three broadcast modes and one individual mode) for efficient data assignment.
RC Array Execution Control Unit
If the main processor directly controls the RC array execution through AMBA AHB, it will cause high overhead in the main processor. In addition, the latency of the control will degrade the performance of the whole system, especially when dynamic reconfiguration is used. So we implement a control unit to control the execution of the RC array every cycle. The RC Array Execution Control Unit (RCECU) receives the encoded data for controlling RC execution from the main processor. The encoded data includes execution cycles, chip select, read/write mode, and addresses of FB and CCU for guaranteeing correct operations of the RC array.
RCM Specification
From profiling result, we find that ME and DCT functions occupymost of the execution time – ME takes about 70% and DCT takes about 7.40%. Specifically, Sum of Absolute Differences (SAD) function called by ME takes about 47.7%. Furthermore, the two functions have regular loops that fit well with the RC array. We determine the RCM structure by analyzing the DCT and ME functions. The structure is similar to Morphosys but the bit-widthof the data bus is extended to 16 and some interconnects between RCs are added for the DCT function. In the case of Morphosys, horizontal and vertical express lanes exist to guarantee connectivity between quadrants but express lanes don’t support concurrent data exchange between symmetrical RCs in the same row or column. Therefore the interconnects are added for removing data arrangement cycles . We do not expect much increase in the area with this modification but need quantitative analysis to see the effect.

[casanovaaggrev]